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73K302L डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Single-Chip Modem - TDK

भाग संख्या 73K302L
समारोह Single-Chip Modem
मैन्युफैक्चरर्स TDK 
लोगो TDK लोगो 
पूर्व दर्शन
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<?=73K302L?> डेटा पत्रक पीडीएफ

73K302L pdf
73K302L
Bell 212A, 103, 202
Single-Chip Modem
DESCRIPTION (continued)
asynchronous communications. The 73K302L is
designed to appear to the systems designer as a
microprocessor peripheral, and will easily interface
with popular one-chip microprocessors (80C51
typical) for control of modem functions through its 8-
bit multiplexed address/data bus or via an optional
serial command bus. An ALE control line simplifies
address demultiplexing. Data communications
occurs through a separate serial port only.
The 73K302L is ideal for use in either free standing
or integral system modem products where multi-
standard data communications is desired. Its high
functionality, low power consumption and efficient
packaging simplify design requirements and
increase system reliability. A complete modem
requires only the addition of the phone line interface,
a modem controller, and RS232 level converter for a
typical system.
Tri-mode capability in one-chip allows full-duplex
Bell 212 and 103 operation or assymetrical Bell
202S operation over the 2-wire switched telephone
network. 202T mode full-duplex operation at 1200
bit/s is also possible when operating on 4-wire
leased lines.
A soft carrier turn-off feature facilitates fast line turn
around when using the 202S mode for half-duplex
applications.
The 73K302L is part of TDK Semiconduct K- Series
family of pin and function compatible single-chip
modem products. These devices allow systems to
be configured for higher speeds and Bell or CCITT
operation with only a single component change.
OPERATION
ASYNCHRONOUS MODE
Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous
fashion. The 73K302L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data at a regular rate. In
asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided
on the TXD pin which normally must be 1200 bit/s
+1.0%, 2.5%. The rate converter will then insert or
delete stop bits in order to output a signal which is
1200 bit/s ± .01% (±0.01% is the required
synchronous data rate accuracy).
The SYNC/ASYNC converter also has an extended
overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the
extended overspeed mode, stop bits are output at
7/8 the normal width.
The serial data stream from the transmit buffer or the
rate converter is passed through the data scrambler
and onto the analog modulator. The data scrambler
can be bypassed under processor control when
unscrambled data must be transmitted. If serial input
data contains a break signal through one character
(including start and stop bits) the break will be
extended to at least 2 times N + 3 bits long (where N
is the number of transmitted bits/character).
Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC converter. The ASYNC/ASYNC
converter will reinsert any deleted stop bits and output
data at an intra-character rate (bit-to-bit timing) of no
greater than 1219 bit/s. An incoming break signal (low
through two characters) will be passed through
without incorrectly inserting a stop bit.
SYNCHRONOUS MODE
The Bell 212A standard defines synchronous
operation at 1200 bit/s. Operation is similar to that of
the asynchronous mode except that data must be
synchronized to a provided clock and no variation in
data transfer rate is allowable. Serial input data
appearing at TXD must be valid on the rising edge of
TXCLK.
TXCLK is an internally derived signal in internal
mode and is connected internally to the RXCLK pin
in slave mode. Receive data at the RXD pin is
clocked out on the falling edge of RXCLK. The
ASYNCH/SYNCH converter is bypassed when
synchronous mode is selected and data is
transmitted out at the same rate as it is input.
DPSK MODULATOR/DEMODULATOR
In DPSK mode the 73K302L modulates a serial bit
stream into di-bit pairs that are represented by four
possible phase shifts as prescribed by the Bell 212A
standards. The baseband signal is then filtered to
reduce intersymbol interference on the bandlimited
2-wire telephone line. Transmission occurs using
either a 1200 Hz (originate mode) or 2400 Hz
(answer mode) carrier. Demodulation is the reverse
of the modulation process, with the incoming analog
2

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भाग संख्याविवरणविनिर्माण
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