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IDT70261L डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM - IDT

भाग संख्या IDT70261L
समारोह HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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<?=IDT70261L?> डेटा पत्रक पीडीएफ

IDT70261L pdf
IDT70261S/L
High-Speed 16K x 16 Dual-Port Static RAM with Interrupt
Industrial and Commercial Temperature Ranges
Description
The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The
IDT70261 is designed to be used as a stand-alone Dual-Port RAM or as
a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
featurecontrolledby CEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 750mW of power.
The IDT70261 is packaged in a 100-pin TQFP.
Pin Configurations(1,2,3)
Index
N/C
N/C
N/C
N/C
I/O10L
I/O11L
I/O12L
I/O13L
GND
I/O14L
I/O15L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
1100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 7675
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10 66
11
IDT70261PF
65
12
PN100(4)
64
13
100-Pin TQFP
63
14
Top View(5)
62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N/C
N/C
N/C
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
N/C
N/C
N/C
3039 drw 02a
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
Right Port
CEL
R/WL
CER
R/WR
OEL
A0L - A13L
OER
A0R - A13R
I/O0L - I/O15L
I/O0R - I/O15R
SEML
SEMR
UBL UBR
LBL LBR
INTL INTR
BUSYL
BUSYR
M/S
VCC
GND
6.242
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
3039 tbl 01

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