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M5M4257L-15 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 256K-Bit DRAM - Mitsubishi

भाग संख्या M5M4257L-15
समारोह 256K-Bit DRAM
मैन्युफैक्चरर्स Mitsubishi 
लोगो Mitsubishi लोगो 
पूर्व दर्शन
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<?=M5M4257L-15?> डेटा पत्रक पीडीएफ

M5M4257L-15 pdf
MITSUBISHI LS1s
MSM42S7L-12, -15, -20
262 144-BIT (262 144-WORD BY I-BIT) DYNAMIC RAM
FUNCTION
The M5M4257L provides, in addition to normal read,
write, and read-modify-write operations, a number of other
functions, e.g., nibble mode, RAS-only refresh, and delayed-
write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation
RAS CAS
Inputs
Iii 0
Row
Column
address address
Read ACT ACT NAC DNC APD APD
Write
ACT ACT ACT VLD APD APD
Read-modify-write
ACT ACT ACT VLD APD APD
AAS-only refresh
ACT NAC DNC DNC APD DNC
Hidden refresh
ACT ACT DNC DNC DNC DNC
CAS before RAS refresh
ACT ACT DNC DNC DNC DNC
Standby
NAC DNC DNC DNC DNC DNC
*Note: ACT: active, NAC: nonactive, ONe: don t care, VLO. valid, APO. applied, OPN. open.
~
'Nibble mode identical except refresh is No, and Nibble mode column address is ONe while togging CAS
Output
Q
VLD
OPN
VLD
OPN
VLD
OPN
OPN
Refresh
YES
YES
YES
YES
YES
YES
NO
Remarks
*
SUMMARY OF OPERATIONS
Addressing
To select one of the 262144 memory cells in the
M5M4257L the 18-bit address signal must be multiplexed
into 9 address signals, which are then latched into the
on-chip latch by two externally·applied clock pulses. First,
the negative-going edge of the row-address-strobe, pulse
(RAS) latches the 9 row-address bits; next, the negative-
going edge of the column-address-strobe pulse (CAS)
latches the 9 column-address bits. Timing of the RAS and
CAS clocks can be selected by either of the following two
methods:
1. The delay time from RAS to CAS td (RAS-CAS) is set
between the minimum and maximum values of the
limits. In this case, the internal CAS control signals are
inhibited almost until td(RAS-CAS) max ('gated CAS'
operation). The external CAS signal can be applied with
a margin not affecting the on-chip circuit operations, e.g.
access time, and the address inputs can be easily changed
from row address to column address.
2. The delay time td(RAS.CAS) is set larger, than the
maximum value of the limits. In this case the internal
inhibition of CAS has already been released, so that the
internal CAS control signals are controlled by the
externally applied CAS, which also controls the access
time.
Data Input
Data to be written into a selected cell is strobed by the later
of the two negative transitions of W input and CAS input.
Thus when the IN input makes its negative transition prior
to CAS input (early write). the data input is strobed by
CAS, and the negative transition of CAS is set as the
reference point for set-up and hold times. In the read-write
or read-modify-write cycles,however, when the IN input
makes its negative transition after CAS, the IN negative
transition is set as the reference point for setup and hold
times.
Data Output Control
The output of the M5M4257L IS In the high-impedance
state when CAS is high. When the memory cycle in progress
is a read, read-modify-write, or a delayed-write cycle, the
data output will go from the high-impedance state to the
active condition, and the data in the selected cell will be
read. This data output will have the same polarity as the
input data. Once the output has entered the active
condition, this condition will be maintained until CAS goes
high, irrespective of the condition of RAS.
The output will remain in the high-impedance state
throughout the entire cycle in an early-write cycle.
These output conditions, of the M5M4257L, which can
readily be' changed by controlling the timing of the write
pulse in a write cycle, and the width of the CAS pulse in a
read cycle, offer capabilities for a number of applications,
as follows.
1. Common I/O Operation
If all write operations are performed in the early-write
mode, input and output can be connected directly to give a
common I/O data bus.
2 Data Output Hold
The data output can be held between read cycles, without
lengthening the cycle time. This enables extremely flexible
clock-timing settings for RAS and CAS.
2-156
• MITSUBISHI
...... ELECTRIC

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