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UPD7802 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER - NEC

भाग संख्या UPD7802
समारोह HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
मैन्युफैक्चरर्स NEC 
लोगो NEC लोगो 
पूर्व दर्शन
1 Page
		
<?=UPD7802?> डेटा पत्रक पीडीएफ

UPD7802 pdf
J'PD7802
PINNa.
1,49-63
2
DESIGNAnON
ABO-AB15
t/>OUT
FUNCTION
(Tri-State, Output) 16-bit address bus.
(Output) .pOUT provides a prescaled outp.ut
c\9ck for use with exte~nal 1/0 devices or
memories. .pOUT frequency is fXTAU2.
PIN DESCRIPTION
3-10 DBO-DB7
11 INTO
12 INTI
13 INT2
14 WAiT
15 Ml
16 WR
17 RD
18-25
26
PCO-PC7
SCK
27 SI
28 SO
29 RESET
30 X2
(Tri-State Input/Output, active high) 8-bit true
bi-directional data bus used for external data
exchanges with I/O and memory.
(Input, active high) Level-sensitive interrupt input.
(Input, active high) Rising-edge sensitive interrupt
input. Interrupts are initiated on low-to-high transi-
tions, providing interrupts are enabled.
(Input) INT2 is an edge sensitive interrupt input
where the desired activation transition is pro-
grammable. By setting the ES bit in the Mask
Register to a I, INT2 is rising edge sensitive. When
ES is set to 0, INT2 is falling edge sensitive.
(Input, active low) WAIT, when active, extends
read or write timing to interface with slower
external memory or I/O. WAIT is sampled at
the end of T2, if active processor enters a wait
stateTw and remains in that state as long as
WAIT is active.
(Output, active high) when active, M1 indicates
that the current machine cycle is an OP CODE
FETCH.
(Tri-State Output, active low) WR, when active,
indicates that the data bus holds valid data. Used
as a strobe ~al for external memory or I/O write
operations. WR goes to the high impedance state
during HALT, HOLD, or RESET.
(Tri-State Output, active low) RD is used as a
strobe to ~e data from external devices onto the
data bus. RD goes to the high impedance state
during HALT, HOLD, and RESET.
(Input/Output) 8-bit I/O configured as a nibble
I/O port or as control lines.
(I nput/Output) SCK provides control clocks for
Serial Port Input/Output operations. Data on the
SI line is clocked into the Serial Register on the ris-
ing edge. Contents of the Serial Register is clocked
onto SO line on falling edges.
(Input) Serial data is input to the processor
through the SI line. Data is clocked into the Serial
Register MSB to LSB with the rising edge of SCK.
(Output) SO is the Serial Output Port. Serial data
is output on this line on the falling edge of SCK,
MSB to LSB.
(Input, active low) RESET initializes the IlPD7801.
(Output) Oscillator output.
31
33-40
41-48
Xl
PAO-PA7
PBO-PB7
(Input) Clock Input
(Output) a-bit output port with latch capability.
(Tri-State Input/Output) a-bit programmable I/O
port. Each line configurable independently as an
input or output.
278

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डाउनलोड[ UPD7802 Datasheet.PDF ]


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