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CD4046BMS डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - CMOS Micropower Phase Locked Loop - Intersil Corporation

भाग संख्या CD4046BMS
समारोह CMOS Micropower Phase Locked Loop
मैन्युफैक्चरर्स Intersil Corporation 
लोगो Intersil Corporation लोगो 
पूर्व दर्शन
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CD4046BMS pdf
CD4046BMS
Phase Comparators
The phase-comparator signal input (terminal 14) can be
direct-coupled provided the signal swing is within CMOS
logic levels (logic “0” 30% (VDD-VSS). logic “1” 70% (VDD
- VSS)]. For smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal input.
Phase-comparator I is an exclusive -OR network; it operates
analogously to an overdriven balanced mixer. To maximize
the lock range, the signal and comparator-input frequencies
must have a 50% duty cycle. With no signal or noise on the
signal input, this phase comparator has an average output
voltage equal to VDD/2. The low-pass filter connected to the
output of phase-comparator I supplies the averaged voltage
to the VCO input, and causes the VCO to oscillate at the
center frequency (fo).
The frequency range of input signals on which the PLL will
lock if it was initially out of lock is defined as the frequency
capture range (2fc).
The frequency range of input signals on which the loop will
stay locked if it was initially in lock is defined as the fre-
quency lock range (2fL). The capture range is the lock
range.
With phase-comparator I the range of frequencies over
which the PLL can acquire lock (capture range) is dependent
on the low-pass-filter characteristics, and can be made as
large as the lock range. Phase-comparator I enables a PLL
system to remain in lock in spite of high amounts of noise in
the input signal.
One characteristic of this type of phase comparator is that it
may lock onto input frequencies that are close to harmonics of
the VCO center-frequency. A second characteristic is that the
phase angle between the signal and the comparator input var-
ies between 0o and 180o, and is 90o at the center frequency.
Figure 1 shows the typical, triangular, phase-to-output
response characteristic of phase comparator I. Typical wave-
forms for a CMOS phase-locked-loop employing phase com-
parator I in locked condition of fo is shown in Figure 2.
VDD
AVERAGE OUTPUT
VOLTAGE
VDD/2
0 90o 180o
SIGNAL-TO-COMPARATOR
INPUTS PHASE DIFFERENCE
FIGURE 1. PHASE-COMPARATOR I CHARACTERISTICS AT
LOW-PASS FILTER OUTPUT
SIGNAL INPUT (TERM. 14)
VCO OUTPUT (TERM 4) =
COMPARATOR INPUT (TERM 3)
PHASE COMPARATOR I
OUTPUT (TERM 2)
VCO INPUT (TERM 9) =
= LOW-PASS FILTER OUTPUT
VDD
VSS
FIGURE 2. TYPICAL WAVEFORMS FOR CMOS PHASE-
LOCKED LOOP EMPLOYING PHASE COMPARA-
TOR IN LOCKED CONDITION OF fo.
Phase comparator II is an edge-controlled digital memory
network. It consists of four flip-flop stages, control gating,
and a three-state output circuit comprising p- and n- type
drivers having a common output node. When the p-MOS or
n-MOS drivers are ON they pull the output up to VDD or
down to VSS, respectively. This type of phase comparator
acts only on the positive edges of the signal and comparator
inputs. The duty cycles of the signal and comparator inputs
are not important since positive transitions control the PLL
system utilizing this type of comparator. If the signal-input
frequency is higher than the comparator-input frequency, the
p-type output driver is maintained ON most of the time, and
both the n and p drivers OFF (3state) the remainder of the
time. If the signal-input frequency is lower than the compara-
tor-input frequency, the n-type output driver is maintained
ON most of the time, and both the n and p drivers OFF (3
state) the remainder of the time. If the signal and comparator
input frequencies are the same, but the signal input lags the
comparator input in phase, the n-type output driver is main-
tained ON for a time corresponding to the phase differences.
If the signal and comparator-input frequencies are the same,
but the comparator input lags the signal in phase, the p-type
output driver is maintained ON for a time corresponding to
the phase difference. Subsequently, the capacitor voltage of
the low-pass filter connected to this phase comparator is
adjusted until the signal and comparator inputs are equal in
both phase and frequency. At this stable point both p- and n-
type output drivers remain OFF and thus the phase compar-
ator output becomes an open circuit and holds the voltage
on the capacitor of the low-pass filter constant. Moreover the
signal at the “phase pulses” output is a high level which can
be used for indicating a locked condition. Thus, for phase
comparator II, no phase difference exists between signal and
comparator input over the full VCO frequency range. More-
over, the power dissipation due to the low-pass filter is
reduced when this type of phase comparator is used
because both the p- and n-type output drivers are OFF for
most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range, independent of the low-pass filter. With
no signal present at the signal input, the VCO is adjusted to
its lowest frequency for phase comparator II. Figure 15
shows typical waveforms for a CMOS PLL employing phase
comparator II in a locked condition.
7-887

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CD4046BMMicropower Phase-Locked LoopNational Semiconductor
National Semiconductor
CD4046BMSCMOS Micropower Phase Locked LoopIntersil Corporation
Intersil Corporation


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