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8T39S04A डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Crystal or Differential to Differential Clock Fanout Buffer - IDT

भाग संख्या 8T39S04A
समारोह Crystal or Differential to Differential Clock Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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8T39S04A pdf
8T39S04A Datasheet
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
Number
Name
Type
Description
1
GND
Power
2
VDDOA
Power
3
QA0
Output
4
nQA0
Output
Power supply ground.
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
5
VDDOA
Power
6
QA1
Output
Output supply pin for Bank QA outputs.
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
7
nQA1
Output
Differential Bank A clock output pair. LVPECL, LVDS or HCSL interface levels.
8
GND
Power
Power supply ground.
9
SMODE0
Input
Pulldown
Output driver select for Bank A and Bank B outputs. See Table 3D for function.
LVCMOS/LVTTL interface levels.
10 VDD Power
11
XTAL_IN
Input
Power supply pin.
Crystal oscillator interface.
12 XTAL_OUT Output
Crystal oscillator interface.
13
REF_SEL0
Input
Pulldown
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A for function.
14
CLK0
Input
Pullup/
Pulldown
Non-inverting differential clock. Internally biased to 0.33VDD.
15
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock. Internal resistor bias to 0.4VDD.
16
REF_SEL1
Input
Pulldown
Input clock selection. LVCMOS/LVTTL interface levels.
See Table 3A for function.
17
GND
Power
18
nQB1
Output
Power supply ground.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
19
QB1
Output
20
VDDOB
Power
21
nQB0
Output
22
QB0
Output
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Output supply pin for Bank QB outputs.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
Differential Bank B clock output pair. LVPECL, LVDS or HCSL interface levels.
23
VDDOB
Power
24
GND
Power
25 nc Unused
Output supply pin for Bank QB outputs.
Power supply ground.
No connect pin.
26
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock. Internal resistor bias to 0.4VDD.
27
CLK1
Input
Pullup/
Pulldown
Non-inverting differential clock. Internally biased to 0.33VDD.
28 VDD Power
29
REFOUT
Output
Power supply pin.
Single-ended reference clock output. LVCMOS/LVTTL interface levels.
30
VDDOREF
Power
Output supply pin for REFOUT output.
31
OE_SE
Input
Pulldown Output enable. LVCMOS/LVTTL interface levels. See Table 3B.
32
SMODE1
Input
Pulldown
Output driver select for Bank A and Bank B outputs. See Table 3D for function.
LVCMOS/LVTTL interface levels.
0
ePAD
Power
Connect ePAD to ground to ensure proper heat dissipation.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
2
May 20, 2016

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