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83948I डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1-to-12 Differential-toLVCMOS/LVTTL Fanout Buffer - IDT

भाग संख्या 83948I
समारोह 1-to-12 Differential-toLVCMOS/LVTTL Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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83948I pdf
83948I Datasheet
Table 1. Pin Descriptions
Number
Name
1 CLK_SEL
2
3
4
5
6
7
8, 12, 16,
20, 24, 28, 32
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
10, 14, 18,
22, 26, 30
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
VDD
GND
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
VDDO
Type
Input
Pullup
Input
Input
Input
Input
Input
Power
Pullup
Pullup
Pulldown
Pullup
Pullup
Description
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Clock enable pin. LVCMOS/LVTTL interface levels.
Output enable pin. LVCMOS/LVTTL interface levels.
Positive supply pin.
Power
Power supply ground.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
25 pF
7
Function Tables
Table 3A. Clock Select Function Table
Control Input
Clock
CLK_SEL
CLK/nCLK
LVCMOS_CLK
0
Selected
De-selected
1
De-selected
Selected
©2016 Integrated Device Technology, Inc
2
May 19, 2016

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