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831752 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Clock Switch - IDT

भाग संख्या 831752
समारोह Clock Switch
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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831752 pdf
831752 Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1
DIR_SEL
Input
Pulldown
Direction control for the FCLK I/O. Works in conjunction with nOEFCLK.
See Table 3 for function. LVCMOS/LVTTL interface levels.
2
3, 10, 14
nOEFCLK
VDD
Input
Power
4, 5 FCLK, nFCLK I/O
6, 11, 15
7
8
9
12, 13
16
GND
CLK
nCLK
nc
nQ, Q
IREF
Power
Input
Input
Unused
Output
Input
Pullup
Pulldown
Pulldown/Pullup
Output enable for the FCLK I/O output. Works in conjunction with
DIR_SEL. See Table 3 for function. LVCMOS/LVTTL interface levels.
Core and output power supply pin.
Differential I/O. Signal direction is controlled by DIR_SEL. Accepts
differential signals when operating as an input. Differential HCSL
signals when operating as an output. Internal source termination can be
disabled. See Table 3 for function.
Power supply ground.
Non-inverting input.
Inverting differential clock input.
No connect.
Differential output pair. HCSL interface levels.
An external fixed precision resistor (475) from this pin to ground
provides a reference current used for the differential current-mode Q
and FCLK outputs.
NOTE: Pullup and pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLDOWN Input Pulldown Resistor
RPULLUP
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. Direction Control Function Table
Input
Input
DIR_SEL nOEFCLK Operation
FCLK Function
0
0
Local clock mode 0. The input signal at CLK is routed to Differential HCSL output with internal 50source
both outputs Q and FCLK.
termination
0 (default)
1 (default)
Local clock mode 1. The input signal at CLK is routed to Output is disabled (high impedance). Internal 50
the output Q.
termination is disabled.
1
X
Common reference clock mode. FCLK is the clock input.
Q is the clock output.
Differential clock input. Internal 50source
termination is disabled as well as output driver and
22.33resistors.
NOTE: X = 0 or 1
©2016 Integrated Device Technology, Inc
2
Revision B June 28, 2016

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