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83058 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Single-Ended Multiplexer - IDT

भाग संख्या 83058
समारोह Single-Ended Multiplexer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
1 Page
		
<?=83058?> डेटा पत्रक पीडीएफ

83058 pdf
83058 Datasheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
Q Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
2, 4, 6, 8, CLK7, CLK6, CLK5,
9, 11, CLK4, CLK3, CLK2,
13, 15
CLK1, CLK0
Input
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
3
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
5
GND
Power
Power supply ground.
7, 10, 14 SEL2, SEL1, SEL0
Input
Pulldown
Clock select input. See Control Input Function Table.
LVCMOS / LVTTL interface levels.
12
V Power
Core and input supply pin.
DD
16 V Power Output supply pin.
DDO
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
C
PD
Power Dissipation Capacitance
(per output)
R Output Impedance
OUT
Test Conditions
V = 3.465V
DDO
V = 2.625V
DDO
V = 1.89V
DDO
V = 3.465V
DDO
V = 2.625V
DDO
V = 1.89V
DDO
Minimum
Typical
4
51
51
18
20
30
7
7
10
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
SEL2
0
0
0
0
1
1
1
1
Control Inputs
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Input Selected to Q
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
©2015 Integrated Device Technology, Inc
2
December 15, 2015

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