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8V74S4622 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Clock Fanout Buffer/Frequency Divider - IDT

भाग संख्या 8V74S4622
समारोह Clock Fanout Buffer/Frequency Divider
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
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8V74S4622 pdf
8V74S4622 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions1
Number
Name
Type
Description
1
SEL1
Input
Pulldown Function select control input. LVCMOS 3.3V interface.
SeeTable 3B for function.
2 IN Input
Differential clock signal non-inverting differential input. Internal termination
50.
3 VT
Differential clock input termination pin for built-in 50termination interface.
See the application information for terminating LVDS and LVPECL input
signals.
4 nIN Input
Differential clock signal inverting differential input.
Internal termination 50.
5
REFSEL
Input
Pulldown Input select control input. LVCMOS 3.3V interface. SeeTable 3A for function.
6 VDD Power
Positive supply voltage (3.3V).
7
CLK
Input
Pulldown Single-ended LVCMOS 3.3V clock signal input.
8
N1
Input
Pullup
Frequency divider control input. LVCMOS 3.3V interface.
9
N0
Input
Pulldown See Table 3C for function.
10
nOE1
Input
Pullup
Output Q1 enable control input. LVCMOS 3.3V interface.
See Table 3D for function.
11
VDDO1
Power
12 Q1 Output
13 nQ1 Output
Positive supply voltage (3.3V) for the Q1 output.
Differential clock output 1. LVDS interface signals.
14
GND
Power
Ground supply voltage (0V). Connect to board GND.
15
nOE0
Input
Pullup
Output Q0 enable control input. LVCMOS 3.3V interface.
See Table 3D for function.
16
VDDO0
Power
17 nQ0 Output
18 Q0 Output
Positive supply voltage (3.3V) for the Q0 output.
Differential clock output 0. LVDS interface signals.
19
GND
Power
Ground supply voltage (0V). Connect to board GND.
20
SEL0
Input
Pulldown Function select control input. LVCMOS 3.3V interface.
See Table 3B for function.
GND
Power
Exposed package ground supply voltage (GND). Connect to board GND.
NOTE: 1. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
k
CLOCK FANOUT BUFFER/FREQUENCY DIVIDER
2
REVISION 1 05/11/15

विन्यास 16 पेज
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भाग संख्याविवरणविनिर्माण
8V74S4622Clock Fanout Buffer/Frequency DividerIDT
IDT


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