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8T74S208C-01 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 2.5 V Differential LVDS Clock Divider and Fanout Buffer - IDT

भाग संख्या 8T74S208C-01
समारोह 2.5 V Differential LVDS Clock Divider and Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
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8T74S208C-01 pdf
8T74S208C-01 Datasheet
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions1
Number
1
Name
ADR1
Type
Input
Pulldown
Description
I2C Address input. LVCMOS/LVTTL interface levels.
2
GND
Power
Ground pin.
3 Q0 Output
4 nQ0 Output
Differential output pair 0. LVDS interface levels.
5 Q1 Output
6 nQ1 Output
Differential output pair 1. LVDS interface levels.
7
GND
Power
Ground pin.
8
VDDO
Power
9 Q2 Output
10 nQ2 Output
Output supply pin.
Differential output pair 2. LVDS interface levels.
11 Q3 Output
12 nQ3 Output
Differential output pair 3. LVDS interface levels.
13 Q4 Output
14 nQ4 Output
Differential output pair 4. LVDS interface levels.
15 Q5 Output
16 nQ5 Output
Differential output pair 5. LVDS interface levels.
17
VDDO
Power
18
GND
Power
Output supply pin.
Ground pin.
19 Q6 Output
20 nQ6 Output
Differential output pair 6. LVDS interface levels.
21 Q7 Output
22 nQ7 Output
Differential output pair 7. LVDS interface levels.
23
GND
Power
Ground pin.
24
FSEL0
Input
Pulldown
Frequency divider select control. See Table 3A for function.
LVCMOS/LVTTL interface levels.
25
FSEL1
Input
Pulldown
Frequency divider select control. See Table 3A for function.
LVCMOS/LVTTL interface levels.
26 IN Input
Termination
27 VT Input
Non-inverting differential clock input. RT = 50termination to VT.
Input for termination. Both IN and nIN inputs are internally terminated 50
to this pin. See input termination information in the applications section.
28 nIN Input
Inverting differential clock input. RT = 50termination to VT.
29 VDD Power
Power supply pin.
30
SDA
I/O
Pullup
I2C Data Input/Output. Input. LVCMOS/LVTTL interface levels.
Output: open drain.
31
SCL
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
32
ADR0
Input
Pulldown I2C Address input. LVCMOS/LVTTL interface levels.
NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
2
August 22, 2016

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