DataSheet.in

8SLVP1208 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - LVPECL Output Fanout Buffer - IDT

भाग संख्या 8SLVP1208
समारोह LVPECL Output Fanout Buffer
मैन्युफैक्चरर्स IDT 
लोगो IDT लोगो 
पूर्व दर्शन
1 Page
		
<?=8SLVP1208?> डेटा पत्रक पीडीएफ

8SLVP1208 pdf
8SLVP1208 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions1
Number
Name
Type
Description
1, 14
2, 3
VEE
Q7, nQ7
Power
Output
Negative supply pins.
Differential output pair. 7 LVPECL interface levels.
4
SEL
Input
Pulldown Reference select control. See Table 3 for function. LVCMOS/LVTTL
interface levels.
5
PCLK1
Input
Pulldown Non-inverting differential LVPECL clock/data input.
6
nPCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock/data input. VCC/2 default when left
floating.
7
8, 15, 28
9
VREF
VCC
PCLK0
Output
Power
Input
Pulldown
Bias voltage reference for the nPCLK inputs.
Power supply pins.
Non-inverting differential LVPECL clock/data input.
10
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock/data input. VCC/2 default when left
floating.
11 nc Unused
Do not connect.
12, 13
Q0, nQ0
Output
Differential output pair 0. LVPECL interface levels.
16, 17
Q1, nQ1
Output
Differential output pair 1. LVPECL interface levels.
18, 19
Q2, nQ2
Output
Differential output pair 2. LVPECL interface levels.
20, 21
Q3, nQ3
Output
Differential output pair 3. LVPECL interface levels.
22, 23
Q4, nQ4
Output
Differential output pair 4. LVPECL interface levels.
24, 25
Q5, nQ5
Output
Differential output pair 5. LVPECL interface levels.
26, 27
Q6, nQ6
Output
Differential output pair 6. LVPECL interface levels.
NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RPULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. SEL Input Selection Function Table1
Input
SEL Operation
0 (default) PCLK0, nPCLK0 is the selected differential clock input
1 PCLK1, nPCLK1 is the selected differential clock input
NOTE 1: SEL is an asynchronous control.
LOW PHASE NOISE, 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
2
REVISION 1 08/28/14

विन्यास 23 पेज
डाउनलोड[ 8SLVP1208 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
8SLVP1204LVPECL Output Fanout BufferIDT
IDT
8SLVP1208LVPECL Output Fanout BufferIDT
IDT


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English