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DSC557-04 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Three Output PCIe Clock Generator - Micrel Semiconductor

भाग संख्या DSC557-04
समारोह Three Output PCIe Clock Generator
मैन्युफैक्चरर्स Micrel Semiconductor 
लोगो Micrel Semiconductor लोगो 
पूर्व दर्शन
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<?=DSC557-04?> डेटा पत्रक पीडीएफ

DSC557-04 pdf
DSC557-04
Crystal-less Three Output PCIe Clock Generator
Specifications (Unless specified otherwise: T=25° C, VDD =3.3V)
Parameter
Supply Voltage1
Supply Current
Supply Current2
(Two HCSL Outputs)
Frequency Stability
Startup Time3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
Condition
Min.
VDD 2.25
IDD
EN pin low outputs are
disabled
EN pin high outputs are
IDD enabled
RL=50 Ω, FO1=FO2=FO3=100 MHz
Includes frequency variations
Δf due to initial tolerance, temp.
and power supply voltage
tSU T=25°C
Typ.
42
100
Max.
3.6
46
Unit
V
mA
±100
±50
5
mA
ppm
ms
VIH
0.75xVDD
-V
VIL - 0.25xVDD
tDA 5 ns
tEN 20 ns
Pull-up on OE pin
40 kΩ
Parameter
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter5
VOH
VOL
tR
tF
f0
SYM
JPER
HCSL Outputs6
Condition
RL=50Ω
Single-Ended
20% to 80%
RL=50Ω, CL= 2pF
Single Frequency
Differential
FO1=FO2= FO3 =100 MHz
Min.
0.725
-
200
2.3
48
Typ.
750
1007
2.5
Jitter, Phase
(Common Clock
Architecture)
Integrated Phase Noise
(Data Clock
Architecture)
TJ PCIe Gen 1.1
JRMS-CCHF
JRMS-CCLF
JRMS-CC
JRMS-DCHF
JRMS-DCLF
JRMS-DC
PCIe Gen 2.1, 1.5MHz to Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
PCIe Gen 2.1, 1.5MHz to Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
Notes:
1. VDD should be filtered with 0.01uf capacitor.
2. Output is enabled if OE pin is floated or not connected.
3. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Connection Diagram define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
6. Contact Sales@Discera.com for alternate output options (LVPECL, LVDS, LVCMOS).
7. Contact Sales@Discera.com for alternative frequency options
8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.
22.7
2.20
0.08
0.37
2.15
0.06
0.32
Max.
-
0.1
400
460
52
86.08
3.18
3.08
1.08
4.08
7.58
1.08
Unit
V
mV
ps
MHz
%
psRMS
psp-p
psRMS
psRMS
psRMS
psRMS
psRMS
psRMS
_____________________________________________________________________________________________________________________________ _________________
DSC557-04
Page 2

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