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8T73S1802 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 1:2 Clock Fanout Buffer and Frequency Divider - Integrated Device Technology

भाग संख्या 8T73S1802
समारोह 1:2 Clock Fanout Buffer and Frequency Divider
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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8T73S1802 pdf
8T73S1802 DATA SHEET
Block Diagram
Pin Assignment
CLK
nCLK
VBB
SEL0 Pullup
SEL1 Pullup
EN Pullup
Bias Generator
VCC-1.3V
Control
÷1
÷2
÷4
÷8
QA
nQA
12 11 10
SEL0 13
9
8 VCCO_QB
GND 14
8T73S1802
7 QB
QB SEL1 15 8XXXXXX 6 GND
EN 16
5 GND
12 3 4
16-pin, 3mm x 3mm VFQFN Package
Pin Description and Pin Characteristic Tables
Table 1. Pin Assignment
Pin Number
Name
Type1
Description
1 VCC Power
2 CLK Input
3
nCLK
Input
Power supply voltage for the device core and the inputs.
Non-inverting differential clock input. Compatible with LVPECL, LVDS
and CML signals.
Inverting differential clock input. Compatible with LVPECL, LVDS and
CML signals.
4 VBB Output
5
GND
Power
Bias voltage generator output. Use to bias the nCLK input in
single-ended input applications. VBB = VCC - 1.3V.
Ground supply voltage (GND) and ground return path. Connect to
board GND (0V).
6
GND
Power
Ground supply voltage (GND) and ground return path. Connect to
board GND (0V).
7 QB Output
LVCMOS clock output QB. LVCMOS/LVTTL interface levels.
If this pin is disabled by connecting its power supply pin VCCO_QB to
GND, QB must be left open or connected to GND.
8
VCCO_QB
Power
Positive supply voltage for the QB output. The QB output (if not
connected) can be disabled by connecting this pin to GND.
9
VCCO_QA
Power
10 QA Output
Positive supply voltage for the QA, nQA output. The QA, nQA output (if
not connected) can be disabled by connecting this pin to GND.
Differential clock output QA. LVPECL interface levels.
If this pin is disabled by connecting its power supply pins VCCO_QA to
GND, QA and nQA must be left open or connected to GND.
11
nQA
Output
Differential clock output QA. LVPECL interface levels.
If this pin is disabled by connecting its power supply pins VCCO_QA to
GND, QA and nQA must be left open or connected to GND.
12
VCCO_QA
Power
Positive supply voltage for the QA, nQA output. The QA, nQA output (if
not connected) can be disabled by connecting this pin to GND.
13
SEL0
Input
60kPullup
Configuration pins. 3-Level interface. See Table 3 for function and Table
4D for interface levels.
1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER
2
REVISION 1 08/31/15

विन्यास 24 पेज
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8T73S18021:2 Clock Fanout Buffer and Frequency DividerIntegrated Device Technology
Integrated Device Technology


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