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8T73S208 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Differential LVPECL Clock Divider and Fanout Buffer - Integrated Device Technology

भाग संख्या 8T73S208
समारोह Differential LVPECL Clock Divider and Fanout Buffer
मैन्युफैक्चरर्स Integrated Device Technology 
लोगो Integrated Device Technology लोगो 
पूर्व दर्शन
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8T73S208 pdf
8T73S208 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
1,
32
ADR1, ADR0
Type
Input
Pulldown
Description
I2C Address inputs. LVCMOS/LVTTL interface levels.
2, 7, 18, 23
3, 4
5, 6
VEE
Q0, nQ0
Q1, nQ1
Power
Output
Output
Negative supply pins.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
8, 17
9, 10
11, 12
13, 14
15, 16
VCCO
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Power
Output
Output
Output
Output
Output supply pins.
Differential output pair 2. LVPECL interface levels.
Differential output pair 3. LVPECL interface levels.
Differential output pair 4. LVPECL interface levels.
Differential output pair 5. LVPECL interface levels.
19, 20
Q6, nQ6
Output
Differential output pair 6. LVPECL interface levels.
21, 22
24,
25
Q7, nQ7
FSEL0,
FSEL1
Output
Input
Pulldown
Differential output pair 7. LVPECL interface levels.
Frequency divider select controls. See Table 3A for function.
LVCMOS/LVTTL interface levels.
26 IN Input
27
VT
Termination
Input
Non-inverting differential clock input. RT = 50termination to VT.
Input for termination. Both IN and nIN inputs are internally terminated 50
to this pin. See input termination information in the applications section.
28 nIN Input
Inverting differential clock input. RT = 50termination to VT.
29 VCC Power
Power supply pin.
30
SDA
I/O
Pullup
I2C Data Input/Output. Input: LVCMOS/LVTTL interface levels. Output:
open drain.
31
SCL
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc.
2
Revision D, June 15, 2016

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