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DSC400 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Low Jitter Crystal-less Clock Generator - Microchip

भाग संख्या DSC400
समारोह Low Jitter Crystal-less Clock Generator
मैन्युफैक्चरर्स Microchip 
लोगो Microchip लोगो 
पूर्व दर्शन
1 Page
		
<?=DSC400?> डेटा पत्रक पीडीएफ

DSC400 pdf
DSC400
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage .......................................................................................................................................... –0.3V to +4.0V
Input Voltage .......................................................................................................................................–0.3V to VDD+0.3V
ESD Protection (HBM) ...............................................................................................................................................4 kV
ESD Protection (MM) ................................................................................................................................................400V
ESD Protection (CDM) ............................................................................................................................................1.5 kV
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Specifications: VDD = 3.3V; TA = +25°C unless otherwise specified.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Supply Voltage (Note 1)
VDD 2.25 — 3.6
V—
Core Supply Current (Note 2) IDDCORE
40 44 mA OE(1:2) = 0. All outputs
disabled.
Frequency Stability
f — — ±25 ppm All temperature and VDD
— — ±50
ranges.
Aging - First Year
Aging - After First Year
fY1
fY2+
— ±5 ppm One year at +25°C
— <±1 ppm/yr Year two and beyond at
+25°C
Start-up Time (Note 3)
tSU — — 5 ms T = +25°C
Input Logic Levels
VIH 0.75 x VDD
V Input logic high
VIL — — 0.25 x VDD
Input logic low
Output Disable Time (Note 4)
tDA
— — 5 ns OE(1:2) transition
from 1 to 0
Output Enable Time (Note 4)
tEN
— — 20 ns OE(1:2) transition
from 0 to 1
Pull-Up Resistor
RPU — 40 — kAll input pins have an
internal pull-up
Note 1:
2:
3:
4:
VDD pins should be filtered with a 0.1 µF capacitor connected between VDD and VSS.
The addition of IDDCORE and IDDIO provides the total current consumption of the device.
tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled.
See the Output Waveform section for more information.
DS20005612A-page 2
2016 Microchip Technology Inc.

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