FX631 डेटा पत्रक PDF( Datasheet डाउनलोड )

डेटा पत्रक - Low-Voltage SPM Detector - CML

भाग संख्या FX631
समारोह Low-Voltage SPM Detector
मैन्युफैक्चरर्स CML 
लोगो CML लोगो 
पूर्व दर्शन
1 Page
<?=FX631?> डेटा पत्रक पीडीएफ

FX631 pdf
Pin Number
FX631 FX631
Xtal/Clock: The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in
conjunction with the Xtal output (see Figure 2); circuit components are on chip. Using this mode
of clock2.o3pPeinraFtiuonnc,titohneDCelsoccrikptOiount pin should be connected directly to the Clock In pin. If a clock
pulse input is employed to the Clock In pin, this pin must be connected directly to VDD (see
FigureX2T).AL The input of the oscillator inverter.
XTALN The output of the oscillator inverter
4 2 Xtal: The output of the on-chip clock oscillator inverter.
CLKIN The input to the internal clock divider circuitry.
5 3 Clock WOuhet:n aA3c.l5o7c9k54s5igMnHazl dceryrsivtaeldisfruosmedt,hitesohonu-cldhbipeXcotanlnoesccteildlaatocrro.sIsf tXhTeAoLn&-cXhTipAoLsacnildlaXtoTrAiLs
used, tshhisoupldinbsehdoiureldctlbyecocnonnencnteedctteodCdLiKreINc.tlNyotootthheer CexlotecrknaInl cpoimn.poTnheisntosuatrpeuntescheosusaldrynboetcbaeusuesed
to clocktheotohtehrerdoesvcicilleasto.r components (capacitor, resistor) are on chip.
When an externally available clock signal is used, it should be inserted at CLKIN. XTAL should
be tied to VDD or Vss and XTAL should be left open circuit.
6 4 Clock In: The 3.579545MHz clock pulse input to the internal clock-dividers. If a clock pulse
input isSeYmSTpEloMyeAdl,otghice iXnptault/Cpilnocwkhiicnhpcuotn(tProinls1w)hsehthoeurldthbeedecvoincenedcetteecdtsto12VKh.zSSePeMFtoignuerse(2lo.gic 1)
or 16Khz SPM tones (logic 0). It has an internal 1 Mohm pull- up resistorD(Dl 2Khz).
8 7 VbeBIAdSe: cTaNohmuEeppGolliIefPuideAtTrpt.MhouePtVOonSfePSgt(haseteivoeenFi-nicgphuuitpr,epa2ons)a.itlioveguinepubtiaasndciorcuutpiturtyr.eHspeeldctiinvetelyrnoaf ltlhyeagtaVinDDa/d2j,utshtiinsgpPinOsShIPould
External components are used in conjunction with the op -amp according to the required level
12 8 VSS: Nesgenastivtiveitsyuapnpdlyderapeiln(dGinNgDo)n. whether the incoming signal is differential or common mode.
VDD TThhee ppoowseitrivseupapnldy,ngeroguantdivaensdigfinltaerl ibniapsutpsintso,reasnpdecthtiveeolyu. tput from, the input gain
13 9 Signal In (+):VSS adjusting signal amplifier. Refer to the graph in Figure 4 for guidance on
BIASsVeottoinagndlebviealsssehnosuiltdiveitaiechs btoe ndaet-ioconuapl lsepd,evciiaficaa1tio.0n@s,Facnadpathcietosr,etloecVtSioSn. of gain
17 10 Signal In (-): adjusting components.
TTFOP TRUE TONE FOLLOWER OUTPUT. This is the pin that responds and de-
18 11 Amp Out:
responds within 4ms of a good tone appearing or disappearing.
19 13 Tone FIot lislotwhuesrliOkeuatpnuetn:vTehloipseoouftpthuet SpProMvitdoense.a logic “0” (Low) for the period of a detected tone,
and a logic “1” (High) for NOTONE detection. See Figure 7.
· logic 0 represents ‘detect’ and logic 1 represents ‘not detect’.
20 14 Packet ModeDOTFuOtpPuTth:isAislotghiec oouuttppuut totfhtahet w‘dielllabyeedavtoanileabfolelloawfeter’rbaloccuk.mulation of 40ms of 'good'
tone has been received. This packet mode tone follower will only respond when a tone
frequenItcwyilol rfessupfofincdiewnht eqnu4a0limtyshoafsgbooedentorneecheaivsebdeefonrrseuceffiivceiednwt ithiminea,ni.ye4. 8amcsuwminudlaotwio.nThoef 4408mss iisn
any 48dmivsid, esdhoinrttoto2n4e‘pbauckrsets’ oorf 2bmresaekascwh i(l1l b6Kehizgnmoordeed). oTr h15is‘poauctkpeutts’porof 2v.id66e7smasloeagcich (012K(Lhozw) for
a detecmteodet)o.nEeacahndpaackloetgricepr1ese(Hntisgh3)2fcoyrcNleOsToOfNSEPdMetferecqtiuoenn.cSy.eTehFeigwuinrdeo7w. is a shifting window,
ie. the 48ms window is assessed every 2ms (16Khz mode) or 2.667ms (12Khz). If the necessary
number of good packets are consecutive, the output will respond in the minimum time of 40ms.
21 15 System: The logic input to select device operation to either 12kHz (logic “1” - High) or 16kHz
(logic “0” - Low) SPM s·ylosgteicm0sr.eTphreisseinnptsutdhetaescta’ annidntleorgnica1l 1reMprespeunlltusp‘nroetsdiestteocrt’(.12kHz).
24 16 VDD: Positive supply rail. A single, stable power supply is required. Critical levels and voltages
within the FX631 are dependant upon this supply. This pin should be decoupled to VSS
by a capacitor mounted close to the pin.
Note that if this device is ‘line’ powered, the resulting supply must be stable. See notes on
Microcircuit Protection from high and spurious line voltages.
2, 3, 7,
9, 10,
11, 14,
15, 16,
22, 23
5, 6,
No internal connection, leave open circuit.

विन्यास 9 पेज
डाउनलोड[ FX631 Datasheet.PDF ]

शेयर लिंक

अनुशंसा डेटापत्रक

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