DataSheet.in

UT54ACTS220 डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - Clock and Wait-State Generation Circuit - Aeroflex Circuit Technology

भाग संख्या UT54ACTS220
समारोह Clock and Wait-State Generation Circuit
मैन्युफैक्चरर्स Aeroflex Circuit Technology 
लोगो Aeroflex Circuit Technology लोगो 
पूर्व दर्शन
1 Page
		
<?=UT54ACTS220?> डेटा पत्रक पीडीएफ

UT54ACTS220 pdf
PIN DESCRIPTION
Pin Number Pin Name
2 CLKOUT
3 CLKOUT
4 CLKIN
6 48MHz
8 DMACK
9 RCS
10 MRST
11 TEST
12 DTACK
13 24MHz
Description
Buffered version of CLKIN.
Inverted version of CLKIN.
Clock Input. This signal can be any arbitrary signal that the user wishes to buffer.
48MHz Clock. The 24MHz clock is created by dividing this signal by two.
DMA Acknowledge. This input is generated by the SμMMIT. When high, this signal will
cause DTACK output to be forced high.
RAM Chip Select. This input is generated by the SμMMIT.
Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal
operation tie MRST to VDD through a resistor.
Test output signal.
Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the
SμMMIT if the user requires one wait state during the memory transfer.
24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling
edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high
whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle ± 5%.
FUNCTIONAL TIMING: Single SμMMIT Wait-State
For both read and write memory cycles, DTACK is an input to the SμMMIT E and SμMMIT LXE/DXE. A non-wait state memory
requires two clock cycles, T1 and T2 of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to a log-
ical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, TW of figure 1. The SμMMIT E and
SμMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the rising
edge of the clock, the SμMMIT E and SμMMIT LXE/DXE extends the memory cycle.
48MHz
24MHz
DMACK
RCS
DTACK
T1 TW
T2
Figure 1. Functional Timing
2

विन्यास 12 पेज
डाउनलोड[ UT54ACTS220 Datasheet.PDF ]


शेयर लिंक


अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
UT54ACTS220Clock and Waut State Generation CircuitAeroflex Microelectronic Solutions
Aeroflex Microelectronic Solutions
UT54ACTS220Clock and Wait-State Generation CircuitAeroflex Circuit Technology
Aeroflex Circuit Technology


भाग संख्याविवरणविनिर्माण
30L120CTSchottky RectifierPFC Device
PFC Device
AT28C010-12DKSpace 1-MBit (128K x 8) Paged Parallel EEPROMATMEL
ATMEL
B20NM50FDN-CHANNEL POWER MOSFETSTMicroelectronics
STMicroelectronics
D8442SD844SavantIC
SavantIC
FAE391-A20AM/FM Automotive Electronic TunerMitsumi
Mitsumi


Index : 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z



www.DataSheet.in    |   2017   |  संपर्क   |   खोज     |   English