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IS42S32800G डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 256Mb SYNCHRONOUS DRAM - ISSI

भाग संख्या IS42S32800G
समारोह 256Mb SYNCHRONOUS DRAM
मैन्युफैक्चरर्स ISSI 
लोगो ISSI लोगो 
पूर्व दर्शन
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IS42S32800G pdf
IS42S32800G, IS45S32800G
DEVICE OVERVIEW
The 256Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V Vdd
and 3.3V Vddq memory systems containing 268,435,456
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 67,108,864-bit bank is orga-
nized as 4,096 rows by 512 columns by 32 bits.
The 256Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 256Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled.  Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 2Mx32x4 BANKS)
CLK
CKE
CS
RAS
CAS
WE
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
12
ROW
ADDRESS
12 LATCH
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
12
12
DATA IN
BUFFER
32 32
DQM0 - DQM3
4
DQ 0-31
DATA OUT
BUFFER
32 32
VDD/VDDQ
Vss/VssQ
4096
4096
4096
4096
MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
BURST COUNTER
COLUMN
ADDRESS BUFFER
BANK CONTROL LOGIC
512
(x 32)
COLUMN DECODER
9
2 Integrated Silicon Solution, Inc. - www.issi.com
Rev. A
07/18/2012

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डाउनलोड[ IS42S32800G Datasheet.PDF ]


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