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IS67WVE2M16EALL डेटा पत्रक PDF( Datasheet डाउनलोड )


डेटा पत्रक - 32Mb Async/Page PSRAM - ISSI

भाग संख्या IS67WVE2M16EALL
समारोह 32Mb Async/Page PSRAM
मैन्युफैक्चरर्स ISSI 
लोगो ISSI लोगो 
पूर्व दर्शन
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IS67WVE2M16EALL pdf
IS66/67WVE2M16EALL/BLL/CLL
General Description
PSRAM products are high-speed, CMOS pseudo-static random access memory developed
for low-power, portable applications. The 32Mb DRAM core device is organized
as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous memory
interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings.
For seamless operation on an asynchronous memory bus, PSRAM products incorporated a
transparent self-refresh mechanism. The hidden refresh requires no additional support
from the system memory controller and has no significant impact on device read/write
performance.
A user-accessible configuration registers (CR) defines how the PSRAM device performs on-
chip refresh and whether page mode read accesses are permitted. This register is
automatically loaded with a default setting during power-up and can be updated at any
time during normal operation.
Special attention has been focused on current consumption during self-refresh. This
product includes two system-accessible mechanisms to minimize refresh current.
Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array
refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts refresh operation altogether and is
used when no vital information is stored in the device. The system-configurable refresh
mechanisms are accessed through the CR.
A0~A20
Address
Decode Logic
Configuration Register
(CR)
2M X 16
DRAM
Memory Array
Input
/Output
Mux
And
Buffers
CE#
WE#
OE#
LB#
UB#
ZZ#
Control
Logic
[ Functional Block Diagram]
Rev. 0D | November 2014
www.issi.com - SRAM@issi.com
DQ0~DQ15
2

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अनुशंसा डेटापत्रक

भाग संख्याविवरणविनिर्माण
IS67WVE2M16EALL32Mb Async/Page PSRAMISSI
ISSI


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